1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of forming stressed fin channel structures for FinFET semiconductor devices and to FinFET devices having such stressed fin structures.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If the voltage applied to the gate electrode is less than the threshold voltage of the device, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the past decades. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently prevent the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. FIG. 1A is a perspective end view of a reference FinFET semiconductor device “A” that is formed above a semiconductor substrate “B.” FIG. 1B is a cross-sectional view of the FinFET device taken where indicated in FIG. 1A. The device A includes a plurality of fins “C,” a schematically depicted gate structure “D,” sidewall spacers “E” and a gate cap layer “F.” In a conventional process flow, the portions of the fins C that are positioned in the source/drain regions may be increased in size or even merged together (not shown in FIG. 1A) by performing one or more epitaxial growth processes. With reference to FIG. 1B, the gate structure D may include a so-called high-k gate insulation layer D1, and a plurality of conductive materials that serve as the gate electrode of the device, e.g., a work-function adjusting metal layer D2 and one or more additional conductive gate electrode materials D3.
In a FinFET device, the gate structure D encloses both sides and an upper surface of the fins C to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating fin cap layer (not shown), e.g., silicon nitride, is positioned at the top of the fins C, and the FinFET device A only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate B so as to reduce the physical size of the semiconductor device. The proximity of the two gates also provides an improvement in the control of the channel electrical parameters. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects. When an appropriate voltage is applied to the gate electrode of the FinFET device A, the surfaces (and the inner portion near the surface) of the fins C, i.e., the substantially vertically oriented sidewalls and the top upper surface of the fins C, become populated with inversion carriers, which contribute to current conduction. In a FinFET device, the “channel-width” is approximately two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly stronger drive currents than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
When forming semiconductor devices in a substrate, isolation regions, such as so-called shallow trench isolation (STI) regions, are typically formed in the substrate and filled with an insulating material so as to electrically isolate adjacent semiconductor devices. One process flow that is typically performed to form FinFET devices involves forming a plurality of trenches in the substrate to define the areas where STI regions will be formed and to define the initial structure of the fins. These trenches are typically formed in the substrate during the same process operation for processing simplicity. The trenches have a target depth that is sufficient for the needed fin height and deep enough to allow formation of an effective STI region. After the trenches are formed, a layer of insulating material, such as silicon dioxide, is formed so as to overfill the trenches. Thereafter, a chemical mechanical polishing (CMP) process is then performed to planarize the upper surface of the insulating material with the top of the fins (or the top of a patterned hard mask). Next, an etch-back process is performed to recess the layer of insulating material between the fins and thereby expose the upper portions of the fins C, which corresponds to the final fin height of the fins C.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Given that the gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 20-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (to create a tensile stress in the channel region for NFET transistors and to create a compressive stress in the channel region for PFET transistors). With respect to planar FET devices, stress engineering techniques typically involve the formation of specifically made silicon nitride layers that are selectively formed above appropriate transistors, i.e., a layer of silicon nitride that is intended to impart a tensile stress in the channel region of a NFET transistor would only be formed above the NFET transistors. Such selective formation may be accomplished by masking the PFET transistors and then blanket depositing the layer of silicon nitride, or by initially blanket depositing the layer of silicon nitride across the entire substrate and then performing an etching process to selectively remove the silicon nitride from above the PFET transistors. Conversely, for PFET transistors, a layer of silicon nitride that is intended to impart a compressive stress in the channel region of a PFET transistor is formed above the PFET transistors. The techniques employed in forming such nitride layers with the desired tensile or compressive stress are well known to those skilled in the art.
For both planar and 3D FET devices, the gate structures, i.e., the gate insulation layer(s) and the gate conductor material(s), may be formed using either so-called “gate-first” or “replacement metal gate” (RMG) techniques which are well known to those skilled in the art. In general, in a gate-first process, the materials that will constitute the gate structure are deposited above the substrate and patterned using known photolithography and etching techniques to define the final gate structure. In a replacement-gate process, an initial “dummy” gate structure is formed above the substrate and processing continues with the dummy gate structure in position, e.g., formation of source/drain regions, performing one or more heating processes, etc. At some point, the dummy gate structure is exposed and removed by performing one of more etching processes, which results in a gate cavity. Thereafter, various deposition processes are performed to deposit the materials of the “replacement gate” in the gate cavity. Additional processing operations such as a chemical mechanical polishing (CMP) and/or an etch process are performed to create the final replacement metal gate structure for the device. As indicated by its name, the replacement metal gate typically includes one or more layers of metal due to the superior performance characteristics exhibited by devices that have metal gates, e.g., improved threshold voltage and so-called “Tiny” characteristics as compared to devices using traditional silicon dioxide/polysilicon gate structures. Typically, the common work-function metals, e.g., TiN, TaC, TaN, TiC, TiAl, etc., that are used in replacement gate structures are very thin, e.g., 1-3 nm. Moreover, such work function metals are typically formed in such a manner that they exhibit a relatively low tensile stress, e.g., typically less than 400 MPa.
The present disclosure is directed to various methods of forming stressed fin channel structures for FinFET semiconductor devices and to FinFET devices having such stressed fin structures.